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AUIRS211(7,8)S
However, in a real inverter circuit, the V S voltage swing does not stop at the level of the negative DC bus, rather it
swings below the level of the negative DC bus. This undershoot voltage is called “negative V S transient”.
The circuit shown in Figure 10 depicts a half bridge circuit with parasitic elements shown; Figures 11 and 12 show
a simplified illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the
power circuit from the die bonding to the PCB tracks are lumped together in L D and L S for each switch. When the
high-side switch is on, V S is below the DC+ voltage by the voltage drops associated with the power switch and the
parasitic elements of the circuit. When the high-side power switch turns off, the load current can momentarily flow
in the low-side freewheeling diode due to the inductive load connected to V S (the load is not shown in these figures).
This current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative
voltage between V S and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the V S
pin).
In a typical power circuit, dV/dt is typically designed to be in the range of 1-5 V/ns. The negative V S transient
voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is
greater than in normal operation.
International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding
applications. An indication of the AUIRS2117(8)s’ robustness can be seen in Figure 13, where there is represented
the IRS2117(8)S Safe Operating Area at V BS =15V based on repetitive negative V S spikes. A negative V S transient
voltage falling in the grey area (outside SOA) may lead to IC permanent damage; viceversa unwanted functional
anomalies or permanent damage to the IC do not appear if negative Vs transients fall inside SOA.
www.irf.com
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? 2008 International Rectifier
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